1. Field of the Invention
The present invention is generally in the field of semiconductors. More specifically, the invention is in the field of bipolar and CMOS device fabrication.
2. Related Art
In Bipolar Complementary-Metal-Oxide-Semiconductor (“BiCMOS”) technology, active area scaling has been utilized to increase the performance of transistors, such as silicon-germanium (“SiGe”) heterojunction bipolar transistors (HBT). However, active area scaling is limited in a conventional BiCMOS integration process as a result of facet formation that occurs during a non-selective epitaxial process that is used for base layer formation. See, e.g., “Lateral Scaling Challenges for SiGe NPN BiCMOS Process Integration.” Materials Science in Semiconductor Processing, Vol. 8 (2005) pp. 313-317 by G. D. U'Ren.
In a conventional BiCMOS integration process, prior to formation of the base layer, a wet etch (e.g., an HF etch) is typically performed to remove a sacrificial oxide layer situated on isolation regions and on an active area between the isolation regions. However, the wet etch results in a recess of the isolation region such that a silicon surface is exposed. As a result, during the subsequent base layer formation, typically involving a non-selective epitaxial deposition, the exposed silicon surface can cause uncontrolled facet formation, which causes an undesirable reduction in the usable area that is available for emitter formation. See, e.g., “Influence of Misfit Strain on {311} Facet Development in Selective Epitaxial Growth of SiGe (100) Grown by Gas Source Molecular Beam Epitaxy.” Thin Solid Films Vol. 365, No. 1, April 2000 pp. 147-150, by G. D. U'Ren, M. S., Goorsky, and K. L. Wang.
In the conventional BiCMOS integration process, active area scaling is sought to minimize the distance between the extrinsic base regions and the collector region of the transistor in the formation of a vertical NPN transistor. A decrease in this distance favorably results in a decrease of the extrinsic base-collector capacitance. Extrinsic base-collector capacitance is one component of the sum total base-collector capacitance, which is inversely related to power gain of the bipolar transistor. Thus, in the conventional BiCMOS integration process, the performance route is well known, namely active scaling, but there exists a physical limitation in the implementation of active scaling due to facet formation at the isolation periphery. Consequently, this route to reaching greater performance of power gain is limited by such an obstacle. Moreover, the thin extrinsic base regions in the conventional bipolar transistor further contribute to the undesirable decrease in power gain in that the thin extrinsic base regions result in a higher base resistance. Thus, it is desirable to reduce the base resistance of the conventional bipolar transistor by, for example, increasing the thickness of the extrinsic base regions.
Thus, there is a need in the art for an improved method of forming a bipolar transistor in a BiCMOS process that provides increased active area scalability as well as promoting minimum extrinsic base resistance.